1. Field of the Invention
The present invention relates to a method for making a nano-stamp and to a method which uses the stamp for producing structured patterns including nano-sized elements on the surface of a substrate for use in nano-scale electronic devices, such as integrated circuits (ICs), information storage devices, nano-photonic and opto-electronic devices, nano-biologic devices, nano-sensors and the like.
2. Description of the Prior Art
Lithography is the key procedure in industrial manufacturing of numerous small-scale devices, such as the semiconductor-based ICs, micro-electro-mechanical (MEMs) devices, and magnetic, optical, and electro-optical devices. In its well-known form, the process of lithography involves covering a given surface with a plastic material, called a xe2x80x9cresistxe2x80x9d, which has the property of changing its atomic structure under exposure to energetic particles of electromagnetic or other type of radiation (ions, electrons, molecules, etc.). Then, an appropriately cut mask is placed on the resist, which is made of material impenetrable to the radiation, followed by exposing this surface through the mask to the flow of one of the above-mentioned types of radiation. Subsequently, the exposed areas of resist are dissolved in a special solution, which does not dissolve the unexposed parts of the polymer. Thus a pattern of polymer-covered and uncovered spots is produced on the surface, which subsequently is exposed to a variety of substances necessary for carrying out diffusion steps.
Modern day ICs, MEMs, and opto-electronic device manufacturing requires smaller and smaller patterns to be manufactured on a variety of substrates, particularly on Si, or SiO2 substrates. Optical lithography has been the key for the industrial production of these devices; however, it is well known in the art of lithography that the resolution of the lithographic process is limited by half a wavelength of the electromagnetic radiation. As the size of the patterns shrinked below one micron, the radiation had to be changed from visible to UV, to soft X-ray. In addition to optical radiation, e-beam, ion-beam, atomic and molecular beam, and atomic scanning probe (ASP) are being investigated for possible applications in the area of industrial mass-production of electronic devices having elements with a characteristic dimension below 1 micron.
All of these technologies suffer from serious drawbacks and none is currently able to mass-produce patterns having elements below 50 nm.
Electron-beam lithography has been shown to achieve 10-nm lithographic resolution. A. N. Broers, J. M. Harper, and W. W. Molzen, Applied Phys. Lett. 33, 392 (1978) and P. B. Fisher and S. Y. Chou, Applied Physics Letters. 62, 2989 (1993) reported this kind of resolution, however their approach cannot be practically adapted for industrial production of nano-size patterns. On the other hand, X-ray lithography does not suffer from this detriment and can have a high throughput at 50 nm lithographic resolution, as was shown by K. Early, M. L. Shattenburg, H. I. Smith in Microelectronic Engineering 11, 317 (1990). However, X-ray lithography has not yet shown its ability to go below 50 nm in an industrial fashion.
Atomic scanning probes have shown lithographic resolution below 10 nm, but this procedure is inherently slow and it is yet to be determined if the ASP can fabricate the nano-patterns with necessary speed for mass production.
Another limitation of currently used approaches to lithography is their inherent complexity and the toxicity of the chemicals used for etching. The liquids used for etching out the patterns require special handling procedure to protect the health of the workers. Large resources are spent on safe disposal of waste products, which drives up the cost of the process.
An alternative approach to lithography is the compressive molding of thermoplastic polymers, a technology that has been around for several decades. One example of this technology is imprinted polymethyl methacrylate (PMMA) structures with a feature size on the order of 10 micrometers for making MEMs parts as disclosed by M. Harmening, W. Bacher, P. Bley, A. El-Kholi, H. Kalb, B. Kowanz, W. Mentz, A. Michel, and J. Mohr in Proceedings of IEEE Micro Electro Mechanical Systems, 202 (1992).
H. Lee and S. D. Senture produced molded micro-mechanical parts from polyester with a few tens of a micrometer on the side as described in Proceedings of 1992 13th IEEE/CHMT International Electronic Manufacturing Technology Symposium, 145.
Finally, S. Y. Chou, in U.S. Pat. No. 5,772,905 discloses a technique, which he calls xe2x80x9cNanoimprint Lithographyxe2x80x9d, that utilizes the compressive molding of thermoplastic polymers approach to further reduce lithographic resolution down to sub-25 nm dimensions. In S. Y. Chou""s approach, there is no need for any type of radiation and for masking the resist polymer. Instead the pattern is produced by pressing the mold, which has a nano-scale pattern of elevations and intrusions, into the polymer. How this pattern is produced on the mold is not specified. It is assumed that there exists a technique to do that. However, except for the highly inefficient ASP approach which requires enormous amounts of time to curve out even the simplest nano-scale patterns, there is currently no technique to fabricate nano-molds in an efficient way.
Examples of analogous and non-analogous structures with small elements and analogous and non-analogous methods for making structures with small elements are disclosed in the following analogous and non-analogous U.S. Patents.
The present invention relates to a method and apparatus for fabrication of nano-stamps which either can be used in a process of nano-imprint lithography to produce nano-scale patterns on a thermoplastic polymeric film covering the surface of a selected substrate, or the nano-stamp can be used in a novel process of nano-stamping, which does away with the use of a resist polymer and with the etching of the substrate covered with the polymer and employs the step of stamping the substrate directly, which is possible due to the very high hardness and atomic-level smoothness of the nano-stamp fabricated by using the procedure and materials described herein.
The methods described herein relates to the fabrication of nano-stamps by a fundamentally different approach than has ever been used in any kind of stamping. It is noted that the technology of stamping has existed for thousands of years, as applied to minting of coins, for example. For those applications, stamps, or molds for stamps were carved, polished, or processed in some other way by using hand-held cutting tools. However, when pattern dimensions shrink down to nano-scale, in particular below 25 nm, the only carving tool available has been ASP, which, as described above, is a notoriously slow and inefficient tool.
To fabricate a tool capable of carving or stamping out patterns below 25 nm in size and potentially below 1 nm, the method of the present invention begins with forming a two-dimensional superlattice on a substrate, the exact nature of which is irrelevant in this case. The technique of forming two-dimensional superlattices has been known for decades. A two-dimensional superlattice comprises layers of dissimilar materials deposited upon each other in an alternating fashion. A number of different techniques have been used to fabricate two-dimensional superlattices in industry, such as physical vapor deposition (PVD) and chemical vapor deposition (CVD). These superlattices are characterized by the fact that the sum of thicknesses of the two alternating layers can be made as small as a few nanometers. In other words, the thickness of each individual layer can be as small as a few atomic units. One example of a two-dimensional superlattice is shown in FIG. 2 herein, where NbN and TiN alternating layers have a thickness of 20 nm. This two-dimensional superlattice was fabricated by using an unbalanced magnetron reactive sputtering technique, which produced coherent interfaces in the superlattices. As stated above, other techniques can be used to achieve similar layering of two materials and both coherent and incoherent interfaces can be used in practicing the methods of the present invention.
The next step of the method is to cut the produced superlattice in a plane perpendicular to the planes of the layers and to polish the produced surface to smooth, preferably atomically smooth finish. After it is polished, the polished surface should be as shown in FIG. 2 herein under TEM observation. This surface then is etched to remove one type of layers to some depth. The resulting grid will have distances between elevations determined by the thickness of the alternate layers of the superlattice. This grid of the nano-stamp then can be used for indenting a surface of a substrate in a direction perpendicular to the plane of grid lines in a surface of a substrate. By turning the grid of the nano-stamp 90 degrees in the plane of the substrate, it is possible to make a square pattern of hills and valleys in the surface of the substrate, which subsequently can be sputtered with some magnetic material, like nickel, for example, to fabricate a magnetic memory-type of device.